/* 
	cache definition of SPU 4-way set associative software cache
	works as follows: 
		each cache line has 128 bytes
		- 4 way associative: each address goes into a set where it has 4 possible cache dest. locations
		  these line are in consecutive order to be able to support cacheline crossing cached memory accesses
		- a write mask is traced which tells which bits of the cache line are mapped and possibly dirty
		- cache is getting flushed after each job chain
		- currently cache location and size is fixed, this might change due to be more flexible

	some stuff is put into macros to ensure inlined code even for debug modes
*/

#ifndef __CACHE_H
#define __CACHE_H
#pragma once







































































































































#endif //__CACHE_H
